Updated 2mo ago
by lcapossio
hdldiagZero
An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram
26 GitHub stars (26)
+3 in 16 days
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| Oct 1 | 0 |
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| Oct 5 | +1 |
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| Oct 8 | +1 |
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| Oct 12 | +1 |
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- 1 skill (1 skills found in its SKILL.md files)
- 1 forks (1 forks)
- 2mo ago last update (Last updated 2mo ago)
Install
Skills CLI
npx skills add lcapossio/hdldiagZero
Asks which agents to install it for. Add -g to install it for every project.
Claude Code
git clone https://github.com/lcapossio/hdldiagZerocp -r "hdldiagZero/skills/hdldiagzero" ~/.claude/skills/
Copies the hdldiagzero skill into ~/.claude/skills/ for every project (use .claude/skills/ for one project).
Plugin
/plugin marketplace add lcapossio/hdldiagZero
Run inside Claude Code if the repository ships a plugin marketplace, then pick plugins from /plugin.
Skills can run code on your machine — read the SKILL.md first.
What it does
In the author's own words, from each skill's SKILL.md.
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hdldiagzero
Generate validated SVG block diagrams for HDL/RTL/FPGA/SoC designs. Use when asked to draw, diagram, sketch, render, or visualize Verilog, SystemVerilog, VHDL, Vivado BD, or LiteX architecture. Produces JSON specs plus SVGs, color-codes clock domains, distinguishes AXI/MM/Lite/Stream and TileLink, and hides clock/reset/JTAG/debug detail by default.
skills/hdldiagzero/SKILL.md on GitHub (opens in a new tab)
No skill matches that filter.
Review before you install
A skill is a set of instructions and scripts your agent will follow, and it can run code on your machine. Read the SKILL.md and any scripts first — this listing is not a security review.