Updated 4mo ago
by phamcuong21478
rtl-skills
Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.
20 GitHub stars (20)
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- 10 skills (10 skills found in its SKILL.md files)
- 6 forks (6 forks)
- 4mo ago last update (Last updated 4mo ago)
Install
Skills CLI
npx skills add phamcuong21478/rtl-skills
Asks which skills and agents to install. Just one: npx skills add phamcuong21478/rtl-skills --skill varch — add -g for every project.
Claude Code
git clone https://github.com/phamcuong21478/rtl-skillscp -r "rtl-skills/skills/varch" ~/.claude/skills/
Copies the varch skill into ~/.claude/skills/ for every project (use .claude/skills/ for one project). Repeat for the other skills listed below.
Plugin
/plugin marketplace add phamcuong21478/rtl-skills
Run inside Claude Code if the repository ships a plugin marketplace, then pick plugins from /plugin.
Skills can run code on your machine — read the SKILL.md first.
What it does
In the author's own words, from each skill's SKILL.md.
-
varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton
skills/varch/SKILL.md on GitHub (opens in a new tab) -
vdebug
Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed
skills/vdebug/SKILL.md on GitHub (opens in a new tab) -
vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file
skills/vdesign/SKILL.md on GitHub (opens in a new tab) -
vdoc
Aggregate all per-module documentation into a single comprehensive IP document
skills/vdoc/SKILL.md on GitHub (opens in a new tab) -
vexplain
Generate documentation for any RTL module from Verilog source files
skills/vexplain/SKILL.md on GitHub (opens in a new tab) -
vfill
Implement Verilog code from an approved design proposal, then lint and simulate
skills/vfill/SKILL.md on GitHub (opens in a new tab) -
vflow
Scan project state to determine phase completion, write flow_status.md, and orchestrate the full RTL design flow from architecture to documentation
skills/vflow/SKILL.md on GitHub (opens in a new tab) -
vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power
skills/vsynth/SKILL.md on GitHub (opens in a new tab) -
vtestgen
Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list
skills/vtestgen/SKILL.md on GitHub (opens in a new tab) -
vtestrun
Run all IP-level testcases from tc_list.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions
skills/vtestrun/SKILL.md on GitHub (opens in a new tab)
No skill matches that filter.
Review before you install
A skill is a set of instructions and scripts your agent will follow, and it can run code on your machine. Read the SKILL.md and any scripts first — this listing is not a security review.
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