analog-agents

In the author's own words, from each skill's SKILL.md.

• adc-analyzer

  ADC characterization orchestrator in the analog-agents project. Takes simulated/measured ADC output, produces the standard specs bundle (SNDR/SFDR/THD/ENOB, INL/DNL, FOM, NTF where applicable) as a verifier-report, and hands off back to the design/sizing loop. TRIGGER when the user asks to characterize an ADC, extract ENOB/INL/DNL from dout/aout, compute Walden/Schreier FOM, analyze Σ-Δ NTF, or c…

  skills/adc-analyzer/SKILL.md on GitHub (opens in a new tab)

• analog-audit

  Audit analog circuit netlists for correctness, quality, and risks. Supports both pre-layout (schematic) and post-layout (extracted) netlists. Post-layout mode filters massive parasitic netlists before auditing. Works without EDA. TRIGGER on: "audit", "review netlist", "check this circuit", "design review", "pre-layout", "post-layout", "post-sim", "extracted netlist".

  skills/analog-audit/SKILL.md on GitHub (opens in a new tab)

• analog-behavioral

  Architect Phase 2: build Verilog-A behavioral models and validate system architecture. Use after analog-decompose to verify top-level specs are achievable before transistor design.

  skills/analog-behavioral/SKILL.md on GitHub (opens in a new tab)

• analog-decompose

  Architect Phase 1: decompose top-level analog spec into sub-block specs. Use when starting a new analog design to select architecture, allocate budgets, define sub-block specs, write testbenches, and create verification plans.

  skills/analog-decompose/SKILL.md on GitHub (opens in a new tab)

• analog-design

  Transistor-level circuit design for one analog sub-block. Produces Spectre netlist with hand-calculation rationale. Use when designing a specific circuit block after architecture is defined.

  skills/analog-design/SKILL.md on GitHub (opens in a new tab)

• analog-evolve

  Self-evolution engine for analog-agents. Reviews completed design sessions to extract lessons, discover new anti-patterns, propose checklist additions, and refine agent prompts. Run after design convergence or project completion. TRIGGER on: "evolve", "what did we learn", "improve skills", "meta-review", "self-improve", or automatically at end of analog-pipeline.

  skills/analog-evolve/SKILL.md on GitHub (opens in a new tab)

• analog-explore

  Explore analog design space without simulation. Compare topologies, sweep parameters with hand calculations, find theoretical limits and Pareto tradeoffs. Use for architecture selection, initial sizing, or understanding design space before committing to EDA time. TRIGGER on: "compare topologies", "explore", "design space", "what are my options", "tradeoff analysis", "Pareto".

  skills/analog-explore/SKILL.md on GitHub (opens in a new tab)

• analog-integrate

  Architect Phase 3: replace behavioral models with verified transistor netlists and run top-level integration verification. Use after all sub-blocks pass L2.

  skills/analog-integrate/SKILL.md on GitHub (opens in a new tab)

• analog-learn

  Interactive analog design learning companion. Explains circuit design decisions step by step with underlying physics. Use when learning analog design, studying a topology, or wanting detailed explanations of design tradeoffs. TRIGGER on: "teach me", "explain", "why does", "how does", "learn", "tutorial", "walk me through", or any educational analog design question.

  skills/analog-learn/SKILL.md on GitHub (opens in a new tab)

• analog-netlist-crawl

  Crawl and analyze post-layout parasitic netlists without running SPICE. Answers "what's the effective resistance from node A to node B across this massive R mesh?", "inside the VREFN mesh, which device pins are electrically farthest apart?", "which nets have the worst coupling?", "where does settling bottleneck?" — by parsing the netlist, building a sparse graph, and solving the resistance Laplac…

  skills/analog-netlist-crawl/SKILL.md on GitHub (opens in a new tab)

• analog-pipeline

  MANDATORY — MUST load this skill when the user mentions: OTA, ADC, PLL, comparator, bandgap, LDO, amplifier, opamp, or any analog/mixed-signal IC design task. Full analog design pipeline: spec -> architecture -> design -> verify -> deliver. Orchestrates analog-decompose, analog-behavioral, analog-design, analog-review, analog-verify, analog-integrate, and analog-wiki skills.

  skills/analog-pipeline/SKILL.md on GitHub (opens in a new tab)

• analog-review

  Cross-model circuit design review with divergence analysis. Sends netlist and rationale to multiple external LLMs for independent audit. Supports minimax-m2.7, qwen-3.6-plus, kimi-k2.5, glm-5.1. Use after analog-design to get independent review before simulation.

  skills/analog-review/SKILL.md on GitHub (opens in a new tab)

• analog-verify

  Pre-simulation review and Spectre simulation verification for analog circuits. Reviews circuit netlist and testbench, runs simulation, produces margin report. Use after analog-design completes a netlist.

  skills/analog-verify/SKILL.md on GitHub (opens in a new tab)

• analog-wiki

  Knowledge graph for analog circuit design. Stores topologies, strategies, corner lessons, anti-patterns, and project cases. Query with consult, add entries, track relationships, archive project cases. Use to build and query design knowledge across projects.

  skills/analog-wiki/SKILL.md on GitHub (opens in a new tab)

• virtuoso-librarian

  Move, clone, package, archive, split, or reorganize Cadence Virtuoso cells and libraries at the design-data level. Use this skill whenever the user wants to: copy a TB to another library, reproduce a sim independently in a fresh library, hand off a design, prepare a tapeout archive, split one TB cell into several, promote a block between libraries, or enumerate a design's full reference hierarchy…

  skills/virtuoso-librarian/SKILL.md on GitHub (opens in a new tab)

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