claude-for-hardware

In the author's own words, from each skill's SKILL.md.

• bare-metal-bringup

  Use when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot, hangs after boot, or faults early; covers trap vectors, MMU/PMP, syscall ABI, and boot ordering

  skills/bare-metal-bringup/SKILL.md on GitHub (opens in a new tab)

• codegen-validation

  Use when building or debugging a compiler backend, codegen, or assembler and you need to prove the generated machine code is correct by executing it on a real CPU or a fast emulator, not just inspecting the output

  skills/codegen-validation/SKILL.md on GitHub (opens in a new tab)

• differential-verification

  Use when verifying a hardware DUT (a CPU core, FPGA, or netlist) against a golden reference model, building coverage-guided fuzzing, or detecting where silicon diverges from a simulator like Spike, an emulator, or SPICE

  skills/differential-verification/SKILL.md on GitHub (opens in a new tab)

• firmware-boot-chain

  Use when building or debugging a firmware and boot chain (RISC-V SBI, UEFI, ACPI, a bootloader handoff like Limine to an OS) or adding measured boot with a TPM, and a stage fails to hand off to the next

  skills/firmware-boot-chain/SKILL.md on GitHub (opens in a new tab)

• fpga-bringup

  Use when loading a bitstream onto a physical FPGA and driving or observing it over JTAG or GPIO, especially bit-banged JTAG from a host like a Raspberry Pi, or when configuration silently fails

  skills/fpga-bringup/SKILL.md on GitHub (opens in a new tab)

• fpga-synthesis-fit

  Use when synthesizing RTL to an FPGA with yosys/nextpnr (ECP5/Lattice and similar), fighting area or routing congestion, measuring Fmax, deciding why a design won't fit or route, or instantiating block RAM; covers the pre-pack vs post-pack metric trap

  skills/fpga-synthesis-fit/SKILL.md on GitHub (opens in a new tab)

• hdl-module-design

  Use when writing, refactoring, or deciding how to test an HDL module, component, or IP block (ROHD, Chisel, SpinalHDL, Verilog, VHDL) and you need it parameterized, validated, and covered by exhaustive tests rather than a one-off

  skills/hdl-module-design/SKILL.md on GitHub (opens in a new tab)

• nix-eda-packaging

  Use when packaging EDA or hardware toolchains in Nix (Yosys, OpenROAD, simulators, vendor tools) and hitting dlopen/plugin/runtime-path failures, or writing derivations and build phases for hardware tooling on aarch64-linux

  skills/nix-eda-packaging/SKILL.md on GitHub (opens in a new tab)

• reference-driven-rohd

  Use when implementing a hardware block, protocol, peripheral, or ISA feature in ROHD and you should ground it in the authoritative spec, existing reference implementations, and reusable libraries you fetch first, instead of writing it from memory

  skills/reference-driven-rohd/SKILL.md on GitHub (opens in a new tab)

• rohd-rtl-gotchas

  Use when building or testing RTL in ROHD (Dart), rohd_bridge, or rohd_hcl and hitting hierarchy-violation errors, "Bad state: No element" at sim setup, co-simulation failures, SystemVerilog emission name mismatches, or unexpected register read latency

  skills/rohd-rtl-gotchas/SKILL.md on GitHub (opens in a new tab)

• rtl-area-timing

  Use when optimizing RTL microarchitecture for area or clock frequency (Fmax), a design is too big to fit or too slow to meet timing, a wide multiply or barrel shifter is the critical path, or a "compute everything and select" datapath is too large

  skills/rtl-area-timing/SKILL.md on GitHub (opens in a new tab)

• silicon-grade-discipline

  Use when writing hardware, firmware, verification, or tooling code that will reach real silicon, and you face a tradeoff between shipping fast and shipping correct; covers failures-should-fail, no over-engineering, no-panic, and test coverage

  skills/silicon-grade-discipline/SKILL.md on GitHub (opens in a new tab)

• soc-integration

  Use when composing an SoC from peripherals and a bus fabric, or when generating device trees, ACPI tables, docs, or pin lists from a hardware description and they keep drifting out of sync

  skills/soc-integration/SKILL.md on GitHub (opens in a new tab)

• tapeout-precheck

  Use when preparing a design for tapeout or an MPW shuttle submission (wafer.space style), running DRC/LVS signoff, packaging the GDS, or deciding whether a physical-verification failure is safe to wave; covers metal-layer and std-cell rules

  skills/tapeout-precheck/SKILL.md on GitHub (opens in a new tab)

No skill matches that filter.

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