Updated 1w ago
by bjwanneng
veriflow-cc
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
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- 1 skill (1 skills found in its SKILL.md files)
- 10 forks (10 forks)
- 1w ago last update (Last updated 1w ago)
Install
Skills CLI
npx skills add bjwanneng/veriflow-cc
Asks which agents to install it for. Add -g to install it for every project.
Claude Code
git clone https://github.com/bjwanneng/veriflow-cccp -r "veriflow-cc/src/claude_skills/vf-rtl" ~/.claude/skills/
Copies the vf-rtl skill into ~/.claude/skills/ for every project (use .claude/skills/ for one project).
Plugin
/plugin marketplace add bjwanneng/veriflow-cc
Run inside Claude Code if the repository ships a plugin marketplace, then pick plugins from /plugin.
Skills can run code on your machine — read the SKILL.md first.
What it does
In the author's own words, from each skill's SKILL.md.
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vf-rtl
Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument. Optional: append `--benchmark` to auto-generate a benchmark report after the pipeline completes.
src/claude_skills/vf-rtl/SKILL.md on GitHub (opens in a new tab)
No skill matches that filter.
Review before you install
A skill is a set of instructions and scripts your agent will follow, and it can run code on your machine. Read the SKILL.md and any scripts first — this listing is not a security review.